Conventionally, frequency modulation (FM) transmitters have been designed using analog phase-locked-loops (PLLs) that include voltage controlled oscillators (VCOs). FIG. 1 is a block diagram of a conventional PLL 80. PLL 80 includes phase detector 70, charge pump 71, lowpass filter 72, VCO 1, and feedback divider circuit 73.
VCO 1 receives control voltage 4 and input signal 90 and generates output signal 75. Feedback divider circuit 73 receives a feedback of output signal 75 and generates divided carrier signal 77. Phase detector 70 receives divided carrier signal 77 and reference clock signal 74 and generates phase difference 78. Charge pump 71 receives phase difference 78 and generates charged phase difference 79. In one example, charge pump 71 transforms phase difference 78 into two signals—commonly referred to as an UP and DOWN controlling switches—to steer current into (or out of) a capacitor to generate a voltage having an average value (i.e., duty cycle) that is proportional to phase difference 78. Lowpass filter 72 receives charged phase difference 79 and generates control voltage 4.
Phase detector 70 compares reference signal 74 and divided output signal 77 and adjusts phase difference 78 such that phase difference 78 has frequency components equal to a sum and a difference of a frequency of reference signal 74 and a frequency of divided output signal 77. Low-pass filter 72 attenuates the sum component of charged phase difference 79 but passes difference component of charged phase difference 79 as control voltage 4. In one aspect, low-pass filter 72 attenuates the high frequency components of the charge pump output to generate control voltage 4. Control voltage 4 controls VCO 1, thereby setting a frequency of output signal 75.
Because lowpass filter 72 attenuates the sum component of charged phase difference 79, only the difference component will be present in control voltage 4, which sets the frequency of output signal 75. Control voltage 4 therefore is proportional to the difference in phase between reference signal 74 and divided carrier signal 77. As such, control voltage 4 will adjust a frequency of output signal 75 such that the frequency of output signal 75 moves closer to a frequency of reference signal 74. Thus, PLL 80 locks the frequency of output signal 75 to the frequency of reference signal 74.
Input signal 90 may be applied to modulate the frequency of output signal 75. That is, input signal 90 may further control VCO 1 such that the frequency of output signal 75 varies according to the input signal within a range around the frequency of reference signal 74.
FIG. 2 shows VCO 1 in more detail. VCO 1 includes varactor 3 connected in parallel with inductor 5. DC control voltage 4 is adjusted to control a capacitance of varactor 3. The capacitance of varactor 3 determines the frequency of output signal 75. Specifically, as the capacitance of varactor 3 increases, the frequency of output signal 75 decreases. Alternatively, as the capacitance of varactor 3 decreases, the frequency of output signal 75 increases.